Transistor level technology remapping

This is a process of combining several cells to form new library cells, and to optimize a transistor level netlist. This can be done algorithmically (e.g. pattern matching) or in an ad-hoc fashion. You can verify your area saving, timing improvement and power consumption reduction after this step.

This article is Tagged in: Physical Design , Remapping , Technology Mapping
Written on 20 May 2010 on May 20, 2010

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