Fdis


Dealing with clock jitter in DDR2/DDR3 based designs


For the past couple of days i have been part of a design that interfaces a DDR/DDR2 memory. But lately after a recent pll model integration the whole scenario changed and i was in the middle of a clock jitter related timing check failure. This led me to do some Google search when i found this interesting 3 part article based on the same title.

Defining clock jitter
DDR2/DDR3 functionality
Clock jitter and statistics

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Srikal said on December 9, 2009 at 3:13 PM

Can you please talk about different types of jitter and significance when we deal with pll's?

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