Fdis


Texas Instruments (TI) Interview Questions


  • How are timing constraints developed?
  • Explain timing closure flow/methodology/issues/fixes.
  • Explain SDF (Standard Delay Format) back annotation/ SPEF (Standard Parasitic Exchange Format) timing correlation flow.
  • Given a timing path in multi-mode multi-corner, how is STA (Static Timing Analysis) performed in order to meet timing in both modes and corners, how are PVT (Process-Voltage-Temperature)/derate factors decided and set in the Primetime flow?
  • With respect to clock gate, what are various issues you faced at various stages in the physical design flow?
  • What are synthesis strategies to optimize timing?
  • Explain ECO (Engineering Change Order) implementation flow. Given post routed database and functional fixes, how will you take it to implement ECO (Engineering Change Order) and what physical and functional checks you need to perform?
Source:
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