Fdis


TCL for EDA - A repository Free TCL/TK tools, scripts for EDA...


http://www.tclforeda.org/
The TCL for EDA project is an open-source repository of TCL/TK tools, applications, scripts and methodological articles. The TCL for EDA project targets different stages of chip design: from Verification to Project Management and up to Synthesis, Static Timing Analysis and Design-for-Test.

Some of their offerings:

Tools:
  • Netedit - Verilog netlist editor/viewer
  • Netman - Verilog netlist manager/viewer
  • Pman - Project manager (allows navigation, viewing and editing of verilog files)
  • TCL-PLI - TCL pli library
Scripts:
  • Verilog Structural Integration Methodology and Scripts - Sounds interesting..
  • Lots of DC, Timing, DFT and verifications scripts!

A very interesting site indeed!

{ 2 Reactions ... read them below or write one }

Anonymous said on March 20, 2009 at 6:40 AM

Looks like the site has disappeared? Too bad, I would like to check it out.

John

Murugavel said on March 20, 2009 at 10:55 AM

You are correct John, the site seems to be experiencing some issues. We can only wait :-)

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