Fdis


Digital Design Interview Questions


Your task is to do the power analysis for a circuit that should send out a one-clock-cycle pulse once every 16 clock cycles. (That is, the output is '0' for 15 clock cycles, then '1' for one cycle, then repeat with 15 cycles of '0' followed by a '1', etc.)

You have been asked to consider three different types of counters: a binary counter, a Gray-code counter, and a one-hot counter. (The table below shows the values from 0 to 15 for Gray-code counting). Your implementation technology is an FPGA where each CLB has a programable combinational circuit and a flip-flop. The combinational circuit has 4 inputs and 1 output.

In a CLB, the capacitive load of the combinational circuit is twice that of the flip-flop.
You may assume that all counters:
  1. are implemented on the same fabrication process
  2. run at the same clock speed
  3. have negligible leakage and short-circuit currents
What is the relative amount of power consumption for the different options?

Decimal Gray
0 0000
1 0001
2 0011
3 0010
4 0110
5 0111
6 0101
7 0100
8 1100
9 1101
10 1111
11 1110
12 1010
13 1011
14 1001
15 1000

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