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Latch based Interview Question


Latch-based designs are sometimes used for high-speed digital circuits. One possible configuration places combinational logic between a pair of latches with opposite polarities (one latch is active high and the other is active low) that use the same clock signal. The two latches given below are intended to be used in such configuration. One of the two designs is an active high latch while the other is an active low latch. Additionally, you know that one of the two designs is a “bad” latch.










  1. Which of the two latches is active high and which is active low?
  2. Which of the two latches is the “bad” latch? Clearly justify your answer.

{ 2 Reactions ... read them below or write one }

Andrés Dj. said on May 21, 2008 at 4:18 AM

In both circuits, the AND gate and the negator and NAND at the bottom form an RS latch. The top input is ~R and the bottom ~S. In Latch A, S=~CLK and R=~D*~CLK. It is therefore active low. In Latch B, the CLK is negated the other way round, so it is active high.

When D is low and CLK is active, both ~R and ~S will be low. In the stable state that's no problem: Q will be low, as it should. But what happens during CLK transitions?

During the inactive-to-active edge, if S were asserted before R, there might be a glitch. That doesn't seem to be a problem, due to the purpose of the circuit. But during the active-to-inactive edge, if R is released before S, the latch will retain the wrong state.

More specifically, the problem appears at the AND gate. Its input will transition from {1,0} to {0,1}. They have to do it through {0,0}, not {1,1}, for proper operation. It depends on the physical implementation, but if gate delays happen to be equal, only Latch B will accomplish that.

Hope I can get the job :) . BTW, great blog!

Rohit said on June 4, 2011 at 6:19 PM

Andres u r wrong because both r latches(follows level triggering) which is given in the problem and your concept includes edge triggering which occurs in flip flops.
My view is that A is active low and B is active high. In D latch :
Table1.
CLK D Q(n+1)
1. 0 X Q(n) no change
2. 1 1 1 set
3. 1 0 0 reset
Latch B satisfy above table and it is active high as o/p changes when clock is high.
In latch A:
Table2.
CLK D Q(n+1)
1. 1 X Q(n)
2. 0 0 0
3. 0 1 1

, so it is active low because o/p changes in absence of clock.
And which one is a bad latch ....?? ans is LATCH A because it contradicts standard table(table1) for D latch. So my dear friend if u have any query , mail me at unikxocizm@gmail.com

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